10G SFP+ LR Optical Transceiver

SKU WST-SFP+LR-x Category Tags , , ,




  • Optical interface compliant to IEEE 802.3ae 10GBASE-LR/LW
  • Compliant with SFP+ MSA
  • Data Rate 10.3125 Gbps
  • 1310nm DFB TOSA and PIN ROSA
  • Applicable for 10 km SMF connection
  • LC duplex receptacle
  • Low power dissipation (<1W)
  • Hot Pluggable
  • All-metal housing for superior EMI performance
  • Built in digital diagnostic Functions
  • Operating case temperature range:
    • Commercial Temperature:0°C~70°C
    • Extended Temperature:-5°C~85°C
    • Industrial Temperature:-40°C~85°C
  • RoHS Compliant


  • 10GBASE-LR 10Gigabit Ethernet
  • High-speed storage area networks
  • Computer cluster cross-connect
  • Custom high-speed data pipes



WaveSplitter’s WST-SFP+LR-x transceivers support the 2-wire serial communication protocol as defined in the SFP+ MSA.

The standard SFP serial ID provides access to identification information that describes the transceiver’s capabilities, standard interfaces, manufacturer, and other information.

Additionally, WST-SFP+LR-x transceivers provide a unique enhanced digital diagnostic monitoring interface, which allows real-time access to device operating parameters such as transceiver temperature, laser bias current, transmitted optical power, received optical power and transceiver supply voltage. It also defines a sophisticated system of alarm and warning flags, which alerts end-users when particular operating parameters are outside of a factory set normal range.

The SFP MSA defines a 256-byte memory map in EEPROM that is accessible over a 2-wire serial interface at the 8 bit address 1010000X (A0h).The digital diagnostic monitoring interface makes use of the 8 bit address 1010001X (A2h), so the originally defined serial ID memory map remains unchanged.

The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller (DDTC) inside the transceiver, which is accessed through a 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL, Mod Def 1) is generated by the host. The positive edge clocks data into the SFP transceiver into those segments of the EEPROM that are not write-protected. The negative edge clocks data from the SFP transceiver. The serial data signal (SDA, Mod Def 2) is bi-directional for serial data transfer.

The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially.

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